The present invention relates generally to memory tests, and more particularly to an improved Memory Built-In-Self-Test (MBIST) design or Logic Built-In-Self-Test (LBIST) design.
A memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. There are a large variety of memory devices in the commercial world nowadays. There are types of memory known as ROM, PROM, EPROM, EEPROM and Flash memory. Each type having unique characteristics, but they all share store nonvolatile data. That is, it is not lost when power is removed. Data stored in these chips is either unchangeable or requires a special operation to change.
Random access memory (RAM) is another best known form of computer memory. RAM is considered “random access” because you can access any memory cell directly if you know the row and column that intersect at that cell. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information—a 0 or a 1. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second.
Larger and more complex logic designs in integrated circuits (ICs) lead to demands for more sophisticated testing to ensure fault-free performance of those ICs. In a simple model, testing of an IC can include applying multiple test patterns to the inputs of a circuit and monitoring its outputs to detect the occurrence of faults. Fault coverage indicates the efficacy of the test patterns in detecting each fault in a universe of potential faults. Thus, if a set of test patterns is able to detect substantially every potential fault, then fault coverage approaching 100% has been achieved.
To facilitate better fault coverage and minimize test cost, automatic test pattern generation (ATPG) can be used to generate the minimum set of patterns while providing reasonable fault coverage. Specifically, in deterministic ATPG, each test pattern is designed to test for the maximum number of faults. Alternatively, and more frequently in current, complex ICs, structures can be added to the design that allow the IC to quickly test itself. These built-in self-test (BIST) structures can include various pattern generators, the most typical being a pseudorandom pattern generator. After the patterns generated are propagated through scan chains in the tested design, the outputs are analyzed to determine if a fault is detected. Memory Built-In-Self-Test (MBIST) refers to a system or method operative to generate patterns to test memories embedded in a computing system by itself.
The high level functional blocks in a memory device integrated with a MBIST system 100 are illustrated in FIGS. 1(a) and 1(b). The MBIST system 100 includes BIST module 102 that contains functional blocks such as address/data generators, one or more comparators 104, and a storage device 106 to save failure information, and one or more memory 108 under test. FIG. 1(a) shows a one-BIST-per-memory configuration, wherein each memory module 108 has a BIST module directly incorporated thereto. The BIST module 102 is responsible for generating suitable control, address, and input data to the memory module 108 under test based on predetermined test patterns. The memory under test will respond with suitable outputs in response to such stimulus. The comparator 104 compares the outputs from the memory with expected values. If the outputs do not match with the expected value, the fail code information is stored in the storage device such as a fail code storage module. The fail code information typically includes the test pattern number, pass number, X- and Y-addresses, and bit number.
FIG. 1(b) shows another configuration by using one BIST module 102 to test more than one memory modules. The operation of such a system is the same as the one in FIG. 1(a) except that the control, address, data inputs, and data outputs are passed from the memory module under test through one or more memory that is not under test if necessary to reach the BIST module 102 for testing. Those signals are normally arranged into one or multiple scan chains so that data can be shifted in and out more efficiently.
As the size of the memory device increases, the size of the fail code storage module may be huge. Especially when the defect density is high, memory capacity is large, or many memories are under test, the BIST module itself can be too expensive to be integrated.
As such, desirable in the art of memory designs are improved designs for a MBIST system.